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Design & Verification Core

Course Instructor SumedhaIT

FREE

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Course Overview

Schedule of Classes

Course Curriculum

3 Subjects

CLASS SCHEDULE FOR ALL BATCHES

2 Learning Materials

JNTU Class Schedule 12th May 2025

JNTU Class Schedule 12th May 2025

Audio

Class Schedule For Hi-Tech City Centre-12th May2025

Class Schedule for Hi-Tech City Centre from 12th May 2025

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DV CORE

381 Exercises168 Learning Materials

Verilog SR

Day 1_2

PDF

Day 3

PDF

Day4_Abstraction Levels

PDF

Day 5_Verilog HDL Syntax and Symantics

PDF

Day 6_7_8_Data Types

PDF

Day 9_Parametered Module Design

PDF

Day 10_11_Verilog Operators

PDF

Day 12_Types of Assignments

PDF

Day 13

PDF

Day 14

PDF

Day 15

PDF

Day 16

PDF

Day 17_18

PDF

Day 19

PDF

Day 20

PDF

Day 21

PDF

Day 22

PDF

Day 23_24

PDF

Day 25_26

PDF

Day 27

PDF

Microarchitecture Design

PDF

Lab Manual

PDF

Verilog_Table of Contents

PDF

System Verilog SR

Day 1

PDF

Day 2_3

PDF

Day 4_5

PDF

Day 6_7

PDF

Taming Testbench Timing Material

PDF

Day 8_9

PDF

Day 10

PDF

Day 11

PDF

Day 12

PDF

Day 13_14

PDF

Day 15_16_17_18

PDF

Day 19

PDF

Day 20_21

PDF

Day 22

PDF

Day 23

PDF

Day 24

PDF

Day 25

PDF

Day 26

PDF

SV Table of Contents

PDF

UVM SR

Day_1

PDF

Day_2

PDF

Day_3

PDF

Day_4

PDF

Day_5

PDF

Day_6

PDF

Day_7

PDF

Day_8

PDF

Day_9

PDF

Day_10

PDF

Day_11

PDF

Day_12

PDF

Day_13

PDF

Day_14

PDF

Day_15

PDF

Day_16

PDF

Day_17

PDF

Day_18

PDF

Day_19

PDF

Day_20

PDF

Day_21

PDF

Day_22

PDF

Day_23

PDF

Day_24

PDF

Day 25

PDF

Day 26

PDF

Day 27

PDF

Day 28

PDF

Day 29

PDF

Day 30

PDF

Day 31

PDF

Day 32

PDF

UVM table of Contents

PDF

Verilog Concepts

Verilog Concepts

PDF

LRM

Doc 1

PDF

Doc 2

PDF

Doc 3

PDF

UVM Cookbook

PDF

SV_book

PDF

SRAM

SRAM

PDF

Arbitration

Arbitration

PDF

FEB DV'25

Assignments

1 Exercises

VNR VJIET Assignments

Assignment 1

Assignment

Course Instructor

tutor image

SumedhaIT

41 Courses   •   12773 Students