Course Overview
Schedule of Classes
Course Curriculum
2 Subjects
Zoicx
0 Exercises • 392 Learning Materials
CF
CF_Day_1_Basic_Electronics.pdf
PDF
CF_Day_2_Basic_Electronics.pdf
PDF
CF_Day_3_Basic_Electronics.pdf
PDF
CF_Day_4_MOSFET_Introduction.pdf
PDF
CF_Day_5_MOSFET_Linear_Region.pdf
PDF
CF_Day_6_MOSFET_Non_Linear_Region.pdf
PDF
CF_Day_7_MOSFET_Saturation_Region.pdf
PDF
CF_Day_8_MOSFET__Characteristics.pdf
PDF
CF_Day_9_EPMOSFET_and_DMOSFET.pdf
PDF
CF_Day_10_Body_Bias_and_MOS_Capacitor.pdf
PDF
CF_DAY_11_Energy_Band_diagrams_of_MOS.pdf
PDF
CF_DAY_12_VT_Equation.pdf
PDF
CF_ Day_13_CMOS_Inverter_.pdf
PDF
CF_Day_14_Static_CMOS_Gate.pdf
PDF
CF_Day_15_CF_MOS_Capacitances.pdf
PDF
CF_Day_16_CMOS_Inverter_VTC.pdf
PDF
CF_Day_17_Propagation_Delay_and_Power_Dissipations.pdf
PDF
CF_DAY_18_short_channel_effects.pdf
PDF
CF_Day_19_Velocity_Saturation_and_sub_threshold_conduction.pdf
PDF
CF_Day_20_Drain_Induced_barrier.pdf
PDF
CF_Day_21_Drain_Induced_barrier_.pdf
PDF
CF_Day_22_Electromigration_and_hot_carrier_effects.pdf
PDF
CF_Total
PDF
DDF
DDF_Day_1_Introduction_Digital_Systems.pdf
PDF
DDF_Day_2_Introduction_Logic _Gates.pdf
PDF
DDF_Day_3_Introduction_K-maps.pdf
PDF
DDF_Day_4_Introduction_Combinational_Circuits.pdf
PDF
DDF_Day_5_Parallel_Adders.pdf
PDF
DDF_Day6_Parallel_Subtractors_and_Multipliers.pdf
PDF
DDF_DAY_7_Multiplexers.pdf
PDF
DDF_DAY_8_Vector_Mux_and_Comparators.pdf
PDF
DDF_DAY_9_Vector_Mux_and_Comparators_.pdf
PDF
DDF_DAY_10_Encoders_and_Decoders.pdf
PDF
DDF_DAY_12_Flip-Flop_Conversions_(12).pdf
PDF
DDF_DAY_11_Introduction_Sequential_Circuits.pdf
PDF
DDF_DAY_13_Flip-Flop_Conversions.pdf
PDF
DDF_DAY_14_Synchronous_Counters.pdf
PDF
DDF_Day15_Asynchronous_Counters.pdf
PDF
DDF_Day16_Shift_Registers_and_Ring_Counter.pdf
PDF
DDF_Day17_FSM___Mealy_and_Moore_State_Diagram_.pdf
PDF
DDF_Day18_FSM___Mealy_and_Moore_Design.pdf
PDF
DDF_Day19__Serial_Adder.pdf
PDF
DDF_DAY_20_PLDs_and_Memories.pdf
PDF
DDF_Total
PDF
DF
DF_Day_1_Design_Flow_1
PDF
DF_Day_2_Design_Flow_2
PDF
DF_Day_3_Design_Flow_3
PDF
DF_Day_4_Design_Flow_4
PDF
DF_Day_5_Design_Flow_5
PDF
DF_Day_6_Design_Flow_6
PDF
DF_Day_7_Design_Flow_7
PDF
DF_Day_8_Design_Flow_8
PDF
DF_Day_9_Design_Flow_9
PDF
DF_Day_10_Design_Flow_10
PDF
DF_Day_11_Design_Flow_11
PDF
DF_Day_12_Design_Flow_12
PDF
DF_Total
PDF
Verilog
Day_1_verilog_ASIC_flow_Introduction_to_HDL_Abstraction_levels
PDF
Day_2_verilog_ASIC_flow_Introduction_to_HDL_Abstraction_levels
PDF
Day_3_Verilog_Basics
PDF
Day_4_Types_of_Modelling_in_Verilog
PDF
Day_5_Types_of_Modeling_in_verilog
PDF
Day_6_Types_of_Modeling_in_Verilog
PDF
Day_7_Verilog_Data_Flow_model+Program_on_operations&Data_types
PDF
Day_8_Verilog_Data_Flow_model+Program_on_operations&Data_types
PDF
Day_9_Verilog_Behavioral_Modeling
PDF
Day_10_Verilog_Behavioral_Modeling
PDF
Day_11_Verilog_Types_of_Assignments
PDF
Day_12_Verilog_Types_of_Assignments
PDF
Day_13_Blocking_and_Non-Blocking_Assignments
PDF
Day_14_Blocking_and_Non-Blocking_Assignments
PDF
Day_15_Verilog_ Functions_Tasks_Test_bench
PDF
Day_16_Verilog_ Functions_Tasks_Test_bench
PDF
Verilog_Total
PDF
SL
SL_Day_1_TCL__Commands_to_start_with_TCL.pdf
PDF
SL_Day_2_TCL_List.pdf
PDF
SL_Day_3_TCL__Loops.pdf
PDF
SL_Day_4_TCL__Decisions.pdf
PDF
SL_Day_5_TCL_Array_variable.pdf
PDF
SL_Day_6_TCL_Special_variables_and_Procedures.pdf
PDF
SL_Day_7_TCL_File_Handling.pdf
PDF
SL_Day_8_TCL_Additional_Commands.pdf
PDF
SL_Day_9_TCL_Additional_Commands.pdf
PDF
SL_Day_1_TCSH_-_Introduction.pdf
PDF
SL_Day_2_TCSH_-_List_Find_Editors.pdf
PDF
SL_Day_3_TCSH_-_Permissions.pdf
PDF
SL_Day_4_TCSH_-_Display_Commands.pdf
PDF
SL_Day_5_TCSH_-_sed.pdf
PDF
SL_Day_6_TCSH_-_awk.pdf
PDF
SL_Day_7_TCSH_-_Shell_Scripting.pdf
PDF
SL_Day_8_Makefile.pdf
PDF
SL_Day_9_Makefile_Copy.pdf
PDF
SL_Total
PDF
SL_Total_Unix
PDF
Synthesis
Synthesis_Day_1
PDF
Synthesis_Day_2
PDF
Synthesis_Day_3
PDF
Synthesis_Day_4_Physical_Design_Flow
PDF
Synthesis_Day_5_Physical_Design_Flow
PDF
Synthesis_Day_6_Inputs_to_Physical_Design_Flow
PDF
Synthesis_Day_7_Inputs_to_Physical_Design_Flow
PDF
Synthesis_Day_8_Lab_Excercise
PDF
Synthesis_Day_9_Lab_Excercise
PDF
Synthesis_Day_10_Inputs_to_Physical_Design_Flow
PDF
Synthesis_Day_11_Synthesis_Flow
PDF
Synthesis_Day_12_Synthesis_Flow
PDF
Synthesis_Day_13_Synthesis_Flow
PDF
Synthesis_Day_14_Synthesis_Flow
PDF
Synthesis_Day_15_RTL_and_Schematic_(Recap)
PDF
Synthesis_Day_16_Lab_Excercise
PDF
Synthesis_Day_17_Lab_Excercise
PDF
Synthesis_Day_18_Lab_Excercise
PDF
Synthesis Total
PDF
FV + DFT
DFT Unit 1 - Introduction
PDF
DFT Unit 2 FaultTypes & D Algorithm
PDF
DFT Unit 3 - Scan Basics
PDF
DFT Unit 4 - Scan Insertion Flow
PDF
DFT Unit 5 - DC Shell scan insertion Lab
PDF
DFT Unit 6 - BScan Introduction
PDF
DFT Unit 7- Memory Types, faults, MBIST , MBISR
PDF
STA
Day_11_SSTA_Types_of_Clocks_and_Timing_Analysis
PDF
Day_12_SSTA_Timing_Analysis_(Contd..)
PDF
Day_13_SSTA_Timing_Analysis_(Contd..)
PDF
Day_14_SSTA_Timing_Paths
PDF
Day_15_SSTA_Timing_Paths
PDF
Day_16_SSTA_Timing_Paths_(continued...)
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Day_17_SSTA_Timing_Paths_(continued...)
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Day_18_SSTA_Timing_Paths_(continued...)
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Day_19_SSTA_Timing_Paths_(continued...)
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Day_20_SSTA_Timing_Paths_(continued...)
PDF
Day_21_SSTA_Timing_Paths_(continued...)
PDF
Day_22_SSTA_Timing_Paths_(continued...)
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Day_23_SSTA_Timing_Paths_(continued...)
PDF
Day_24_SSTA_Timing_Paths_(continued...)
PDF
Day_25_SSTA_Synthesis_Flow_Using_Design_Compiler
PDF
Day_26_SSTA_Synthesis_Flow_Using_Design_Compiler
PDF
STA_Total
PDF
P&CTSL
P&CTSL_Day_1
PDF
P&CTSL_Day_2
PDF
P&CTSL_Day_3
PDF
P&CTSL_Day_4
PDF
P&CTSL_Day_5
PDF
P&CTSL_Day_6
PDF
P&CTSL_Day_7
PDF
P&CTSL_Day_8
PDF
P&CTSL_Day_9
PDF
P&CTSL_Day_10
PDF
P&CTSL_Day_11
PDF
P&CTSL_Day_12
PDF
P&CTSL_Day_13
PDF
P&CTSL_Day_14
PDF
P&CTSL_Day_15
PDF
P&CTSL_Day_16
PDF
P&CTSL_Day_17
PDF
P&CTSL_Day_18
PDF
P&CTSL_Day_19
PDF
P&CTSL_Day_20
PDF
P&CTSL_Day_21
PDF
P&CTSL_Day_22
PDF
P&CTSL_Day_23
PDF
P&CTSL_Day_24
PDF
P&CTSL_Day_25
PDF
P&CTSL_Day_26
PDF
P&CTSL_Day_27
PDF
P&CTSL_Day_28
PDF
P&CTSL_Day_29
PDF
P&CTSL_Day_30
PDF
P&CTSL_Day_31
PDF
P&CTSL_Day_32
PDF
P&CTSL_Day_33
PDF
P&CTSL_Day_34
PDF
P&CTSL_Day_35
PDF
P&CTSL_Day_36
PDF
P&CTSL_Day_37
PDF
P&CTSL_Day_38
PDF
P&CTSL_Day_39
PDF
P&CTSL_Day_40
PDF
P&CTSL_Day_41
PDF
P&CTSL_Day_42
PDF
P&CTSL_Day_43
PDF
P&CTSL_Day_44
PDF
P&CTSL_Day_45
PDF
P&CTSL_Day_46
PDF
P&CTSL_Day_47
PDF
P&CTSL_Day_48
PDF
P&CTSL_Day_49
PDF
P&CTSL_Day_50
PDF
P&CTSL_Day_51
PDF
P&CTSL_Day_52
PDF
P&CTSL_Day_53
PDF
P&CTSL_Day_54
PDF
P&CTSL_Day_55
PDF
P&CTSL_Day_56
PDF
P & CTSL Total
PDF
R&CFL
RCFL Total
PDF
PNR (RPTOP)
LP
LP_Day_1
PDF
LP_Day_2
PDF
LP_Day_3
PDF
LP_Day_4
PDF
LP_Day_5
PDF
LP_Day_6
PDF
LP_Day_7
PDF
LP_Day_8
PDF
LP_Day_9
PDF
LP_Day_10
PDF
LP_Day_11
PDF
LP_Day_12
PDF
LP_Day_13
PDF
LP_Day_14
PDF
LP_Day_15
PDF
LP_Day_16
PDF
LP_Day_17
PDF
LP_Day_18
PDF
LP_Day_19
PDF
LP_Day_20
PDF
LP_Day_21
PDF
LP_Day_22
PDF
LP_Day_23
PDF
LP_Day_24
PDF
LP_Day_25
PDF
LP_Day_26
PDF
LP_Day_27
PDF
LP_Day_28
PDF
LP_Day_29
PDF
LP_Day_30
PDF
LP_Day_31
PDF
LP_Day_32
PDF
LP_Day_33
PDF
LP_Day_34
PDF
LP_Day_35
PDF
SSTA Student Reference (Old)
PD Material -day 7
PDF
PD Material -day 9
PDF
PD Material -day 16
PDF
PD Material -day 17
PDF
PD Material -day 29
PDF
PD Material -day 36
PDF
PD Material -day 38
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PD Material -day 39
PDF
PD Material -day 46
PDF
PD Material -day 47
PDF
PD Material -day 48
PDF
PD Material -day 58
PDF
PD Material -day 59
PDF
PD Material -day 66
PDF
PD Material -day 67
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PD Material -day 68
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PD Material -day 69
PDF
PD Material -day 76
PDF
PD Material -day 77
PDF
PD Material -day 79
PDF
PD Material -day 86
PDF
PD Material -day 87
PDF
PD Material -day 1
PDF
PD Material -day 1
PDF
PD Material -day 2
PDF
PD Material -day 2
PDF
PD Material -day 3
PDF
PD Material -day 3
PDF
PD Material -day 6
PDF
PD Material -day 8
PDF
PD Material -day 11
PDF
PD Material -day 11
PDF
PD Material -day 12
PDF
PD Material -day 12
PDF
PD Material -day 14
PDF
PD Material -day 14
PDF
PD Material -day 17 to 28
PDF
PD Material -day 19
PDF
PD Material -day 21
PDF
PD Material -day 21
PDF
PD Material -day 21
PDF
PD Material -day 31
PDF
PD Material -day 31
PDF
PD Material -day 32
PDF
PD Material -day 37
PDF
PD Material -day 31
PDF
PD Material -day 32
PDF
PD Material -day 37
PDF
PD Material -day 46
PDF
PD Material -day 49 to 58
PDF
PNR Student Reference
Day_21_PNR_SR
PDF
Day_22_23_24_26_PNR_SR
PDF
Day_27_PNR_SR
PDF
Day_28_29_PNR_SR
PDF
Day_31_32_PNR_SR
PDF
Day_33_PNR_SR
PDF
Day_34_PNR_SR
PDF
Day_36_37_38_PNR_SR
PDF
Day_39_PNR_SR
PDF
Day_41_42_43_44_PNR_SR
PDF
Day_46_PNR_SR
PDF
Day_47_48_49_PNR_SR
PDF
Day_51_PNR_SR
PDF
Day_52_53_54_PNR_SR
PDF
Day_56_57_PNR_SR
PDF
Day_58_69_PNR_SR
PDF
Day_71_PNR_SR
PDF
Day_72_73_74_PNR_SR
PDF
Day_76_PNR_SR
PDF
Day_77_78_79_PNR_SR
PDF
Day_81_82_PNR_SR
PDF
Day_83_84_PNR_SR
PDF
Day_86_87_PNR_SR
PDF
Day_88_PNR_SR
PDF
Day_89_PNR_SR
PDF
Routing -Notes
PDF
Crosstalk-Notes
PDF
CTS-Notes
PDF
EMIR
PDF
LEC
PDF
PV
PDF
Low Power Design
PDF
PNR OUTPUT ECO FLOW
PDF
IC Compiler II MCMM Command Classification
PDF
SL Student Reference
SL-TCL Material-Day 1
PDF
SL-TCL Material-Day 3
PDF
SL-TCL Material-Day 4
PDF
SL-TCL Material-Day 5
PDF
SL-TCL Material-Day 6
PDF
SL-TCL Material-Day 7
PDF
SL-TCL Material-Day 8
PDF
SL Material-Unix-Day1
PDF
SL Material-Unix-Day5
PDF
SL Material-Unix-Day6
PDF
SL Material-Unix-Day7
PDF
SL Material-Unix-Day8
PDF
SL Material-Linux &Unix OS-Chapter 2
PDF
SL Material-OS-Chapter 1
PDF
SL Material-Shell Terminal-Chapter 4
PDF
SL Material-Tiger vnc installation -chapter - 3
PDF
SL - TCL MATERIAL - DAY 2
PDF
SL Material-Unix-Day2
PDF
SL Material-Unix-Day3
PDF
SL Material-Unix-Day4
PDF
SL - TCL & Unix _ Index (Table of Contents)
PDF
DDF Student Reference
DDF Material-Day 1
PDF
DDF Material-Day 2
PDF
DDF Material-Day 3
PDF
DDF Material-Day 4
PDF
DDF Material-Day 5
PDF
DDF Material-Day 6
PDF
DDF Material-Day 7
PDF
DDF Material-Day 8
PDF
DDF Material-Day 9
PDF
DDF Material-Day 10
PDF
DDF Material-Day 11
PDF
DDF Material-Day 12
PDF
DDF Material-Day 13
PDF
DDF Material-Day 14
PDF
DDF Material-Day 15
PDF
Networks
PDF
DV_DDF_Day_1
PDF
DV_DDF_Day_2
PDF
DV_DDF_Day_3
PDF
DV_DDF_Day_4
PDF
Clock
PDF
DDF_Index (Table of Contents)
PDF
CF Student Reference
CF_Week_1_SR
PDF
CF_Week_2_SR
PDF
CF_Week_4_SR
PDF
CF_Week_3_SR
PDF
CF_Day_0
PDF
CF_FinFet
PDF
Diodes_Zener and Avalanche_BJT_MOSFET_current mirror_differential pair
PDF
SSTA Student Reference (New)
STA DAY 1
PDF
STA DAY 2
PDF
STA DAY 3
PDF
STA DAY 4
PDF
STA DAY 5
PDF
STA DAY 6
PDF
STA DAY 7
PDF
STA DAY 8
PDF
STA DAY 9
PDF
STA DAY 10
PDF
STA DAY 11_12
PDF
STA DAY 13_14_15
PDF
STA DAY 16_17
PDF
STA DAY 18_19_20
PDF
STA DAY_21
PDF
STA DAY 22
PDF
STA DAY 23
PDF
STA DAY 24
PDF
STA DAY 25_26
PDF
STA DAY 27_28
PDF
STA DAY 29
PDF
Useful Techniques to Avoid Timing Closure Challenges During IP Flattening of SOC STA
PDF
Multicycles
PDF
SSTA Index 1 to 21 Days
PDF
SSTA Index 22 to 29 Days
PDF
Latch
PDF
DPL
DPL_Total
PDF
Fab
Fab
PDF
Zoicx_New
6 Exercises • 211 Learning Materials
CF FR
1_CF_MOSFET – An Introduction
PDF
2_MOSFET – Linear Region
PDF
3_MOSFET – Non Linear Region
PDF
4_MOSFET – Saturation Region
PDF
5_MOSFET – Characteristics
PDF
6_EPMOSFET and DMOSFET
PDF
7_CF_ Body Bias and MOS Capacitor
PDF
8_CF_Energy Band diagrams of MOS
PDF
9_CF_VT Equation
PDF
10_CF_CMOS Inverter
PDF
11_CF_Static CMOS Gate
PDF
12_CF_MOS Capacitances
PDF
13_CF_CMOS Inverter VTC
PDF
14_CF_Propagation Delay and Power Dissipations
PDF
15_short channel effects
PDF
16_ Velocity Saturation and sub threshold conduction
PDF
17_Drain Induced barrier
PDF
18_Electromigration and hot carrier effects
PDF
19_Finfet
PDF
CF SR
1_Mosfet
PDF
2_Threshold voltage components
PDF
3_CMOS
PDF
4_Short Channel Effects
PDF
5_Finfet
PDF
DDF FR
1_DDF_Combinational Circuits.
PDF
2_DDF_Adders
PDF
3_DDF_Subtractors
PDF
4_DDF_Multiplexers
PDF
5_DDF_Vector Multiplexer
PDF
6_DDF_Encoder
PDF
7_DDF_Flipflops
PDF
8_DDF_Flip flop convertions
PDF
9_DDF_Counters
PDF
10_DDF_Synchronous Counters
PDF
11_DDF_Shift Registers
PDF
12_DDF_Sequence_Detector
PDF
13_DDF_Sequence_Detector
PDF
14_DDF_Serial Adder
PDF
15_DDF_Memories
PDF
DDF SR
1_DDF_Combinational Circuits
PDF
2_DDF_Adders
PDF
3_DDF_Subtractors
PDF
4_DDF_Multiplexer
PDF
5_DDF_Vector Multiplexer
PDF
6_DDF_Encoder
PDF
7_DDF_Flipflops
PDF
8_DDF_Flip flop convertions
PDF
9_DDF_Counters
PDF
10_DDF_Asynchronous Counters
PDF
11_DDF_Shift Registers
PDF
12_DDF_Sequence_Detector
PDF
13_DDF_Sequence_Detector
PDF
14_DDF_Serial Adder
PDF
15_DDF_Memories
PDF
DF FR
Design Flow_FR
PDF
DF SR
Design Flow
PDF
Design Flow_New
PDF
Fab FR
1_Fab_Introduction to Fabrication Process
PDF
2_Fab_Si wafer_Czochralski process
PDF
3_Fab_Oxide growth, Etching, types of etching, Diffusion and Ion Implantation
PDF
4_Fab_Metallization and Packaging
PDF
5_Fab_CMOS Fabrication steps
PDF
Fab SR
1_Fab_Introduction to Fabrication Process
PDF
2_Fab_Si wafer_Czochralski process
PDF
3_Fab_Oxide growth, Etching, types of etching, Diffusion and Ion Implantation
PDF
4_Fab_Metallization and Packaging
PDF
5_Fab_CMOS Fabrication steps
PDF
UNIX/TCL FR
1_TCL_Introduction to TCL
PDF
2_TCL_List Operations
PDF
3_TCL_Loops
PDF
4_TCL_Decisions
PDF
5_TCL_Arrays
PDF
6_TCL_Procedures
PDF
7_TCL_File Handling
PDF
8_TCL_Additional Commands
PDF
1_UNIX_Start with Basic commands on the shell
PDF
2_UNIX_Shell commands
PDF
3_UNIX_Permissions upon files and commands for System information
PDF
4_UNIX_Useful operations upon files
PDF
5_UNIX_Important processing commands - Stream Editor (sed)
PDF
6_UNIX_Important processing commands_awk
PDF
7_UNIX_Writing a Shellscript
PDF
8_UNIX Makefile
PDF
UNIX/TCL SR
1_UNIX_Start with Basic commands on the shell
PDF
2_UNIX_Shell commands
PDF
3_UNIX_Permissions upon files and commands for System information
PDF
4_UNIX_Useful operations upon files
PDF
5_UNIX_Important processing commands - Stream Editor (sed)
PDF
6_UNIX_Important processing commands_awk
PDF
7_UNIX_Writing a Shellscript
PDF
8_UNIX Makefile
PDF
Linux and Unix OS
PDF
Operating systems
PDF
Shell Terminal
PDF
Tiger vnc installation
PDF
1_TCL_Introduction to TCL
PDF
2_TCL_List Operations
PDF
3_TCL_Loops
PDF
4_TCL_Decisions
PDF
5_TCL_Arrays
PDF
6_TCL_Procedures
PDF
7_TCL_File Handling
PDF
8_TCL_Additional Commands
PDF
Verilog FR
Verilog_HDL
PDF
Verilog SR
Verilog HDL
PDF
Synthesis FR
1_2_3_4_SYN_Pre_Synthesis
PDF
5_SYN_Synthesis_Introduction
PDF
6_SYN_Types_of_Synthesis
PDF
7_SYN_Back_end_design_flow
PDF
8_SYN_SDC
PDF
9_SYN_Reports_output_files
PDF
Synthesis SR
1_2_3_4_SYN_Pre_Synthesis
PDF
5_SYN_Synthesis_Introduction
PDF
6_SYN_Types_of_Synthesis
PDF
7_SYN_Back_end_design_flow
PDF
8_SYN_Timing_Constraint_Commands
PDF
9_SYN_Synthesis_Reports_and_Output_files
PDF
Synthesis Lab Guide (ALU Design)
Lab Guide_ALU_Synthesis
PDF
FV&DFT FR
1_Introduction
PDF
2_Faulttypes_DAlgo
PDF
3_Scan
PDF
4_Scan_Insertion_FLow
PDF
5_DC_Tool_Scan_insertion_Lab
PDF
6_BSCAN
PDF
7_Memory_Types_MBIS_
PDF
Introduction_ToolGui
PDF
FV&DFT SR
1_Design For Test Introduction
PDF
2_FAULT MODELING AND DESIGN CHANGES
PDF
3_SCAN BASICS
PDF
4_SCAN CHAIN
PDF
5_SCAN INSERTION TOOL INTRODUCTION
PDF
6_BSCAN INTRODUCTION
PDF
7_DIFFERENT TYPES OF MEMORIES
PDF
FV_LEC_Introduction_Tool
PDF
LP - Low power FR
LP - Low power SR
low_power_design_lecture_1
PDF
low_power_design_lecture_2
PDF
low_power_design_lecture_3
PDF
low_power_design_lecture_4
PDF
low_power_design_lecture_5
PDF
low_power_design_lecture_6
PDF
low_power_design_lecture_7
PDF
STA FR
10_STA_PVT_Libs
PDF
11_STA_OCV
PDF
12_STA_PBA_GBA
PDF
13_STA_Clock
PDF
14_STA_sta_vs_dta
PDF
15_STA_Timing_closure
PDF
16_STA_Delays
PDF
STA SR
10_STA_PVT_Corners_lib
PDF
11_STA_OCV
PDF
12_STA_PBA_GBA
PDF
13_STA_Clock
PDF
14_STA_sta_vs_dta
PDF
15_STA_Timing_closure
PDF
16_STA_Delays
PDF
DPL_Lab Guide (RPTOP Initialize + Macro Placement)
DPL_Lab Guide
PDF
DPL_lab_Guide_new
PDF
P&CTS FR
13_Placement Bounds
PDF
14_Group Paths_Congestion Analysis and Fixes
PDF
15_Placement legality and Sanity Checks
PDF
16_Goals of CTS and Optimization
PDF
17_Antenna Effect
PDF
P&CTS SR
13_Placement Bounds
PDF
14_Group Paths_Congestion Analysis and Fixes
PDF
15_Placement legality and Sanity Checks
PDF
16_Goals of CTS and Optimization
PDF
17_Antenna Effect
PDF
R&CF FR
18_Routing and Optimization
PDF
19_Special Cells - Decap_Filler_Tap
PDF
20_DEF_GDS_NETLIST_LEF
PDF
21_ECO
PDF
22_PV_Timing Analysis_DRC_LVS_Antenna_ERC
PDF
23_Low Power_Clock Gating_UPF
PDF
24_EMIR
PDF
25_DPT_Multi Vt
PDF
R&CF SR
18_Routing and Optimization
PDF
19_Special Cells - Decap_Filler_Tap
PDF
20_DEF_GDS_NETLIST_LEF
PDF
21_ECO
PDF
22_PV_Timing Analysis_DRC_LVS_Antenna_ERC
PDF
23_Low Power_Clock Gating_UPF
PDF
24_EMIR
PDF
25_DPT_Multi Vt
PDF
PNR Lab Guide (ALU Design)
Lab Guide_ALU_PNR
PDF
Project (RPTOP, SPI Slave, ARM)
RPTOP_Lab Guide
PDF
Lab Guide_SPI_Slave
PDF
Lab Guide_Synthesis_RPTOP
PDF
DPL FR
1_Recap_of_Design_Flow_with_Intro_to_PD
PDF
2_Inputs_to_Physical_Design_Flow
PDF
3_Partitioning
PDF
4_Floorplan Initialization_IO Placement_Macro_Placement
PDF
5_Technology_MMMC
PDF
6_Synopsys_ICC2_Compiler_Introduction
PDF
7_IO Pads_Bonding Pads
PDF
8_Types of Macros and Macro Placement
PDF
9_End Cap and Boundary Cells
PDF
10_Types of Power and Planning Power Grid
PDF
11_Well Tap Cells
PDF
12_Floorplan Checks and Placement Blockages
PDF
DPL SR
1_Recap_of_Design_Flow_with_Intro_to_PD
PDF
2_Inputs_to_Physical_Design_Flow
PDF
3_Partitioning
PDF
4_Floorplan Initialization_IO Placement_Macro_Placement
PDF
5_Technology_MMMC
PDF
6_Synopsys_ICC2_Compiler_Introduction
PDF
7_IO Pads_Bonding Pads
PDF
8_Types_of_Macros_and_Macro_Placement
PDF
9_End Cap and Boundary Cells
PDF
10_Types of Power and Planning Power Grid
PDF
11_Well Tap Cells
PDF
12_Floorplan Checks and Placement Blockages
PDF
Zoicx_Pre Test
Zoicx Assessment 1
Exercise
Zoicx Assessment_2
Exercise
Zoicx Assessment 3
Exercise
Zoicx Assessment 4
Exercise
Zoicx Assessment 5
Exercise
Assignments
CF_Assignment
Assignment
Course Instructor
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